Key takeaways

  • Cerebras’s WSE‑3 Turbo packs four trillion transistors and 250 PFLOPS (sparse) on a single 46,225 mm² wafer.
  • The CS‑4 rack houses three WSE‑3 Turbo wafers, delivering 750 PFLOPS of AI compute and 129.6 PB/s of on‑chip memory bandwidth.
  • NVIDIA’s GB300 NVL72 aggregates 72 Blackwell Ultra GPUs for up to 1,440 PFLOPS (sparse) but consumes 132–142 kW per rack.
  • Cerebras cites a twice‑as‑close power‑conversion architecture that cuts board‑level loss, enabling higher frequencies without a disclosed rack‑level power figure.
  • When measured on token‑generation throughput, Cerebras reports >4,400 tokens / s per user on a 120‑billion‑parameter model, a 30× gain over a comparable GPU rack.
  • The architectural shift to a rear‑mounted, liquid‑cooled “wafer‑scale backpack” reduces component count by roughly 50 % and shortens deployment from days to hours.

Introduction

We see the AI compute landscape converging on two very different integration philosophies. NVIDIA’s GB300 NVL72 treats a rack as a bundle of 72 discrete GPUs, each with its own memory stacks and NVLink fabric. Cerebras, by contrast, slides a single 4‑trillion‑transistor wafer‑scale engine into a modular rack‑backpack and pushes the clock higher through tighter power delivery. The question for investors and engineers is how those choices translate into compute per megawatt and the physical footprint of a modern AI data‑center.

How Cerebras raises the wafer clock

Cerebras describes the WSE‑3 Turbo as the largest AI chip ever built, measuring 46,225 mm² and integrating 900,000 AI‑optimized cores. The company says the chip’s point‑of‑load power conversion sits 0.5 mm from the silicon, roughly 100 × closer than the typical 50 mm distance on conventional GPU boards. Cerebras states this “nearly eliminates board‑level power loss” and “enables the delivery of twice as much power to the WSE‑3T, enabling higher operating frequencies and faster token generation.”

Comparative specification snapshot

FeatureNVIDIA GB300 NVL72Cerebras CS‑4 (3 × WSE‑3T)
Compute (sparse)1,440 PFLOPS (NVFP4)750 PFLOPS (system)
Dense compute1,080 PFLOPS (NVFP4)–
Wafer size / die area–46,225 mm² per wafer
Transistor count–4 trillion per wafer
On‑chip SRAM–44 GB per wafer
Memory bandwidth–129.6 PB/s (system)
Per‑wafer bandwidth–43.2 PB/s memory, 53.5 PB/s fabric
I/O bandwidth–7.2 Tb/s (system)
I/O latency–2 µs wafer‑to‑wafer
Rack power (nominal)132–142 kWNot disclosed, but power‑loss reduction claims double available power
Weight1,580 kg–
Cooling method~90 % liquidDirect‑to‑chip liquid cooling inside backpack

All numbers are taken directly from the manufacturers’ specification pages or press releases.

Compute‑per‑watt considerations

NVIDIA lists a nominal rack draw of 132–142 kW for the GB300 NVL72. The same source states the rack delivers up to 1,440 PFLOPS of sparse FP16 performance, equating to roughly 10 PFLOPS per megawatt.

Cerebras does not publish a rack‑level power figure for the CS‑4. However, the company emphasizes that moving the DC‑DC conversion “just 0.5 mm away from the processor” “nearly eliminates board‑level power loss” and “enables the delivery of twice as much power to the WSE‑3T”. The implication is a higher compute‑per‑watt ratio, even though an exact numeric density cannot be derived from public data.

Impact on data‑center architecture

Modular backpack vs traditional chassis

Cerebras’s wafer‑scale backpack consolidates the wafer, liquid‑cooling manifolds, power conversion and high‑speed I/O into a single 3‑D module attached to the rear of the rack. Cerebras says this design “folds … into a compact 3D package with 50% fewer components” and “reduces deployment time from days to hours.” By contrast, the GB300 NVL72 occupies a 48U cabinet with 18 compute trays, nine NVSwitch trays and eight power shelves, weighing 1,580 kg.

Power distribution topology

Cerebras attributes the frequency gain to the same point‑of‑load design described above: with power delivery “just 0.5 millimeters away from the processor,” the company says CS‑4 “nearly eliminates board‑level power loss,” which it credits with “enabling higher operating frequencies and faster token generation.” NVIDIA’s rack, by comparison, routes power through conventional server back‑planes and relies on external chillers that reject about 90 % of its heat into liquid.

Interconnect latency

Cerebras advertises a 2 µs wafer‑to‑wafer latency, which the company says enables “more than 1,000 tokens per second on models exceeding 50 trillion parameters”. NVIDIA’s NVLink domain provides 130 TB/s intra‑rack bandwidth, but crossing the chassis boundary drops to roughly 400 Gb/s, a reduction of more than 30× according to an industry analysis.

Real‑world throughput claims

Cerebras reports that a CS‑4 rack can sustain over 4,400 tokens per second per user on the GPT‑OSS‑120B model. The same workload on a comparable GPU rack, the company says, takes 30 seconds to produce the same output – a 30× speedup. Additionally, the CS‑4 is marketed as delivering up to 10× more throughput per watt than its predecessor, the CS‑3.

Investment and deployment outlook

Cerebras announced a 165 MW AI data‑center with Compute Nordic in Mikkeli, Finland, signaling that the company expects to scale the CS‑4 platform across hyperscale facilities. The modular rack design, together with the claimed power‑loss reductions, suggests a potentially lower total‑cost‑of‑ownership for operators who prioritize footprint and energy efficiency.

By contrast, NVIDIA’s GB300 NVL72 still requires a substantial mechanical infrastructure (weight, liquid‑cooling plant, power distribution) to support its 140 kW draw. The higher raw PFLOPS count may make it attractive for workloads that need massive dense GPU parallelism, but the inter‑node bandwidth ceiling could limit scaling for trillion‑parameter models.

Conclusion

Cerebras’s over‑clocked WSE‑3 Turbo demonstrates that moving power conversion close to the silicon and embracing a wafer‑scale backpack can produce a system that, on a per‑rack basis, delivers comparable PFLOPS while shaving latency and component complexity. NVIDIA’s GB300 NVL72 still leads in aggregate sparse FP16 throughput, but it does so at a higher disclosed power envelope and with a more traditional rack layout. For data‑center planners, the trade‑off hinges on whether compute density, latency and deployment speed outweigh the raw PFLOPS advantage of a massive GPU farm.

Sources

This article was researched and fact-checked against the following sources: